In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the wafer to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates such as semiconductor wafers. In conventional CMP, a wafer carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the wafer against the polishing pad. The pad is optionally moved (e.g., rotated) relative to the substrate by an external driving force. Simultaneously therewith, a polishing solution (e.g., a chemical composition, a “slurry” or other fluid medium) is flowed onto the substrate and between the wafer and the polishing pad. The wafer surface is thus polished by the chemical and mechanical action of the pad surface and slurry in a manner that selectively removes material from the substrate surface.
Different improvements to CMP systems have been proposed to improve the CMP process. One such improvement relevant to the invention described below is set forth in U.S. Pat. No. 6,116,992, which discloses a CMP system that utilizes a retaining ring to used to keep the wafer in place and to put pressure on an annular portion of the polishing pad surrounding the wafer to reduce edge polish non-uniformities.
A problem encountered when planarizing a wafer is the introduction of “defects” onto the wafer surface. These defects include scratches, pits, cracking, dishing, erosion, particles, etc. The presence of defects on a wafer surface is referred to as “defectivity.” In the manufacturing of semiconductor devices, defectivity is known to reduce product yield, which in turn reduces profit. Accordingly, techniques that reduce defectivity during CMP processing tend to improve device yield, which in turn makes the manufacturing of semiconductor devices more profitable.